library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity memoria is
	port(
		CE_neg     : in std_logic;  -- neg significa negado (risco em cima)
		entrada_REM: in std_logic_vector (3 downto 0); -- endereco de memoria proveniente da REM
	   saida_bw   : out std_logic_vector(7 downto 0):="00000000" -- saida para o barramento w
	);
end memoria;

architecture arquitetura of memoria is
begin
	process(CE_neg,entrada_REM)
	begin
		if(CE_neg='0') then -- escrita no barramento habilitada
			case entrada_REM is
				when "0000" => saida_bw <= "00001001"; -- endereco 0000 => LDA 9H
				when "0001" => saida_bw <= "00011010"; -- endereco 0001 => ADD AH
				when "0010" => saida_bw <= "00011011"; -- endereco 0010 => ADD BH
				when "0011" => saida_bw <= "00101100"; -- endereco 0011 => SUB CH
				when "0100" => saida_bw <= "1110XXXX"; -- endereco 0100 => OUT
				when "0101" => saida_bw <= "1111XXXX"; -- endereco 0101 => HLT
				when "0110" => saida_bw <= "XXXXXXXX"; -- endereco 0110
				when "0111" => saida_bw <= "XXXXXXXX"; -- endereco 0111
				when "1000" => saida_bw <= "XXXXXXXX"; -- endereco 1000
				when "1001" => saida_bw <= "00010000"; -- endereco 1001 => 10H
				when "1010" => saida_bw <= "00010100"; -- endereco 1010 => 14H
				when "1011" => saida_bw <= "00011000"; -- endereco 1011 => 18H
				when "1100" => saida_bw <= "00100000"; -- endereco 1100 => 20H
				when "1101" => saida_bw <= "XXXXXXXX"; -- endereco 1101
				when "1110" => saida_bw <= "XXXXXXXX"; -- endereco 1110
				when "1111" => saida_bw <= "XXXXXXXX"; -- endereco 1111
				when others => saida_bw <= "00000000";
			end case;
		end if;
	end process;

end arquitetura;
